High functionalization and miniaturization have been remarkable for electronic equipment represented by portable information terminals and communications terminals. A flip chip system in which IC chips are directly mounted on the surface of a multilayer printed wiring board has been adopted as a manner of mounting IC chips used for these electronic equipment on a multilayer printed wiring board in high density. One known multilayer printed wiring board is equipped with a core board, a build-up layer formed on the core board, and mounting electrodes on which an IC chip is mounted via soldering bumps on the upper surface of the build-up layer. Here, as a core board used is a material formed by molding epoxy resin, BT (bismaleimide/triazine) resin, polyimide resin, polybutadiene resin, phenol resin or the like together with reinforcing material such as glass fiber or the like. The thermal expansion coefficient of the core substrate thus formed is equal to about 12 to 20 ppm/° C. (30 to 200° C.), and is equal to about four times or more of the thermal expansion coefficient of silicon of IC chips (about 3.5 ppm/° C.). Accordingly, in the case of the above-described flip chip system, when temperature variation caused by heating of an IC chip is repeated, soldering bumps and the IC chip (an interlayer insulating layer is made porous) may be broken due to the difference in the thermal expansion amount and thermal contraction amount between the IC chip and the core board.
In order to solve this problem, there has been proposed a multilayer printed wiring board in which a stress relaxation layer having a low coefficient of elasticity is provided on the build-up layer, mounting electrodes are provided on the upper surface of the stress relaxation layer, and a conductor pattern on the build-up layer and the mounting electrodes are connected to each other by conductor posts (JP 58-28848 A and JP 2001-36253 A). For example, as shown in FIG. 12 of the disclosure of JP 2001-36253 A, a multilayer printed wiring board 100 includes a low-elasticity layer 140 that is laminated on the upper surface of a build-up layer 130, and a conductor pattern 132 on the upper surface of the build-up layer 130 and mounting electrodes 152 formed on the upper surface of the low-elasticity layer 140 that are connected to each other by a via hole 150. Furthermore, in disclosure of JP 2001-36253 A, thermoplastic resin such as polyolefin resin or polyimide resin, thermosetting resin such as silicone resin, modified epoxy resin containing rubber such as NBR or the like is used as a specific example of the resin for forming the low-elasticity layer 140.